1. Field of the Invention
This invention relates to a reference voltage generating circuit, and also to a voltage reducing circuit for a semiconductor device.
2. Description of the Related Art
FIG. 4 shows a conventional reference voltage generating circuit 4 which is used in a voltage reducing circuit 5. The reference voltage generating circuit 4 includes a series circuit of a resistor R.sub.11, and three N-channel transistors NT.sub.11, NT.sub.12 and NT.sub.13 which is connected between a power supply (Vcc) and the ground level. The gate of each of the transistors NT.sub.11 -NT.sub.13 is connected to the drain of the respective transistor. A reference voltage V.sub.ref which is the sum of the threshold values V.sub.th of the transistors NT.sub.11 -N.sub.13 is output from the node of the resistor R.sub.11 and the transistor NT.sub.11 to the inverting input of a differential amplifier OP.sub.11. The output of the amplifier OP.sub.11 is coupled to the gate of a P-channel transistor PT.sub.11 of the voltage reducing circuit 5. The source of the transistor PT.sub.11 is connected to the power supply (Vcc). A reduced voltage V.sub.int is supplied to a load Z from the drain of the transistor PT.sub.11. The node T.sub.11 of the transistor PT.sub.11 and the load Z is connected to the non-inverting input of the amplifier OP.sub.11. The conductance of the transistor PT.sub.11 is controlled by the output of the amplifier OP.sub.11 so that the potential difference (V.sub.int -V.sub.ref) becomes approximately zero. Therefore, the level of the reduced voltage V.sub.int is substantially equal to that of the reference voltage V.sub.ref (i.e., the sum of the threshold values V.sub.th of the transistors NT.sub.11 -NT.sub.13) without depending upon the power supply V.sub.cc and the load Z.
The threshold values V.sub.th of the transistors NT.sub.11 -NT.sub.13 are uneven because of variations in characteristics caused in the manufacturing process. As a result, the reference voltage V.sub.ref greatly varies for each reference voltage generating circuit, and consequently the reduced voltage V.sub.int widely varies for each voltage reducing circuit. Hereinafter, such a variation of the reference voltage V.sub.ref or reduced voltage V.sub.int is referred to as "the manufacturing variation".
As shown in FIG. 3, the threshold value V.sub.th of a transistor is large at a low temperature, with a result that both the reference voltage V.sub.ref and reduced voltage V.sub.int increase as the temperature drops (namely, these voltages have a negative temperature coefficient). This causes a problem in that, when MOS transistors with the gate length of 1 .mu.m or less are used as the load Z, the reliability of such MOS transistors is impaired. That is, the short gate length increases the electric field strength, thereby allowing hot carriers to be generated. Hot carriers tend to be generated more easily as the field strength increases or the temperature decreases, and adversely affect the reliability of such micro-sized MOS transistors. As mentioned above, in the conventional reference voltage generating circuit (and hence in the conventional voltage reducing circuit), the reference voltage V.sub.ref (and the reduced voltage V.sub.int) increases as the temperature drops, resulting in that the generation of hot carriers is accelerated. This produces a detrimental effect to the reliability of micro-sized MOS transistors, especially at a low temperature.
Some reference voltage generating circuits which generate a reference voltage with a reduced or zero temperature coefficient have been proposed (for example, Japanese Patent Publications (Kokai) Nos. 61(1986)-169,920, 63(1988)-258,108, and 2(1990)-75,010). However, these improved circuits cannot generate a reference voltage with a positive temperature coefficient.